1. Field
Embodiments relate to an interconnection structure and an electronic device employing the same and, more particularly, to an interconnection structure for an integrated circuit (IC) and an electronic device employing the same.
2. Description of the Related Art
In general, a semiconductor device may include a plurality of bulk transistors arranged two-dimensionally on a substrate. The bulk transistors may be scaled down to increase an integration density of the semiconductor device. With developments of photolithography processes and exposure equipment used therefore, a size of the bulk transistors may have somewhat scaled down. Despite the reduction in the size of the bulk transistors, however, there may be a specific technical limit to increasing the integration density of the semiconductor device including the two-dimensionally arranged bulk transistors.
Furthermore, to configure an integrated circuit (IC), discrete devices, e.g., transistors, may be electrically connected using interconnections. With an increase in the integration density of the semiconductor devices, the discrete devices may be downscaled and a width of the interconnections and an interval therebetween may be gradually decreased.
Reductions in the width of the conductive interconnections and the interval therebetween may lead to not only an increase in the electrical resistance of the interconnections but also to an increase in parasitic capacitance between the interconnections. Therefore, the increases in the electrical resistance and parasitic capacitance of the interconnections may result in a reduction of the transmission rate of electrical signals applied to the interconnections.